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Cover image for product 1119314135
Keser
ISBN: 978-1-119-31413-4
Hardcover
528 pages
March 2019, ©2018, Wiley-IEEE Press
List Price: 145.00 USD
17,400,000 IRR / 13,050,000 IRR افزودن به سبد
  • Description
  • Table of Contents
  • Author Information

Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges 

Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons.

Filled with contributions from some of the field’s leading experts, Advances in Embedded and Fan-Out Wafer Level Packaging Technologies begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. This valuable text:

  • Discusses specific company standards and their development results
  • Relates its content to practice as well as to contemporary and future challenges in electronics system integration and packaging

Advances in Embedded and Fan-Out Wafer Level Packaging Technologies will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research. 

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